Currently, as processor units capable of implementing various data processing, products which are referred to as so-called CPUs (Central Processing Units) and MPUs (Micro Processor Units) have been practically utilized. In a data processing system that employs such a processor unit, various application programs with a plurality of instruction codes described therein and various data to be processed are stored in a memory device. The processor unit sequentially reads out the instruction codes and the data to be processed from the memory device to execute a plurality of operation processing one by one. For this reason, one processor unit can implement various data processing. However, in data processing, since it is necessary to sequentially execute a plurality of operation processing one by one, the processor unit reads an instruction code from the memory device for each sequential processing. For this reason, it is difficult to execute complex data processing accompanying a plurality of operation processing with one processor unit at high speed.
On the other hand, when data processing to be executed is limited to one in advance, the logic is formed by a hardware circuit (which is referred to as hard-wired logic) so as to execute the limited data processing. It is not thereby necessary for the processor unit to sequentially read a plurality of instruction codes from the memory device and sequentially execute a plurality of operation processing one by one. For this reason, it is possible to execute the limited data processing at high speed. However, only one data processing can be executed (which lacks in versatility).
In a data processing system in which an application program to be executed can be switched, various data processing will be executed. However, a hardware configuration is fixed, so that it is difficult to execute data processing at high speed. On the other hand, in a logic circuit formed of hardware, it is possible to execute data processing at high speed. However, an application program capable of being executed cannot be changed. Only one data processing can be thereby executed.
A reconfigurable device occupies an intermediate position between these two extreme examples. This device can be reconfigured to a different predetermined configuration as necessary. Accordingly, the reconfigurable device will provide the possibility of a computer that changes hardware resources so that a current computational need is satisfied, by an appropriate reconfiguration.
A reconfigurable device includes a plurality of small-scale functional blocks arranged in a matrix form. In response to an application program, operations of the functional blocks and mutual connecting relationships among operators connected by programmable wiring resources are varied. When an application program to be executed is changed, a hardware configuration of the configurable device changes. For this reason, the configurable device can execute various data processing. Further, in the configurable device, the small-scale functional blocks respectively execute operation processing in parallel. Data processing can be thereby executed at high speed.
As the reconfigurable device of which a hardware configuration changes corresponding to software, a device disclosed in Patent Document 1 (JP Patent Kokai Publication No. JP-P-2003-76668A) and a device disclosed in Patent Document 2 (JP Patent Kokai Publication No. JP-P-2001-312481A) are known. As a specific configuration example of wiring resources for the reconfigurable device, a description in Patent Document 3 (JP Patent No. 3496661) is referred to. As measures when configuration information in a configuration information memory of the reconfigurable device becomes incorrect, descriptions in Patent Document 4 (JP Patent Kokai Publication No. JP-A-2-032620), Patent Document 5 (JP Patent Kokai Publication No. JP-A-5-327477), and Patent Document 6 (JP Patent Kokai Publication No. JP-P-2006-344223A) are referred to.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-P-2003-76668A[Patent Document 2]    JP Patent Kokai Publication No. JP-P-2001-312481A[Patent Document 3]    JP Patent No. 3496661[Patent Document 4]    JP Patent Kokai Publication No. JP-A-2-032620[Patent Document 5]    JP Patent Kokai Publication No. JP-A-5-327477[Patent Document 6]    JP Patent Kokai Publication No. JP-P-2006-344223A